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3-BIT 4:1 MUX-LATCH
SY10E256 SY100E256
FEATURES
s 950ps max. data to output s Extended 100E VEE range of -4.2V to -5.5V s s s s 850ps max. latch enable to output Separate select controls Differential outputs Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K input pulldown resistors s Fully compatible with Motorola MC10E/100E256 s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E256 offer three 4:1 multiplexers followed by latches with differential outputs designed for use in new, high-performance ECL systems. Separate Select controls are provided for the leading 2:1 mux pairs (see block diagram). When the Latch Enable (LEN) is at a logic LOW, the latch is transparent and output data is controlled by the multiplexer select controls. A logic HIGH on LEN latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.
BLOCK DIAGRAM
D0a D0b D0c D0d
PIN CONFIGURATION
VCCO
18 17 16
D1b
D1a D2d
D2c D2b
D E NR
Q0 Q0
SEL1A SEL1B
26 27 28 1 2 3 4
25 24 23 22 21 20 19
D2a
D1a D1b D1c D1d
Q2 Q2 VCC Q1 Q1 VCCO Q0
D E NR
Q1 Q1
SEL2 VEE LEN MR D1c
TOP VIEW PLCC J28-1
15 14 13 12
SEL1A SEL1B SEL2 LEN MR
PIN NAMES
Pin D0x-D2x SEL1A, SEL1B SEL2 LEN MR Q0, Q0-Q2, Q2 VCCO Function Parallel Data Inputs First-stage Select Inputs Second-stage Select Input Latch Enable Master Reset Data Outputs VCC to Output
D0d VCCO Q0
Rev.: C
D0a D0b D0c
D1d
D2a D2b D2c D2d
D E NR
Q2 Q2
5
6
7
8
9
10 11
Amendment: /1
1
Issue Date: February, 1998
Micrel
SY10E256 SY100E256
TRUTH TABLE
Pin SEL2 SEL1A SEL1B State H H H Operation Output c/d Data Input d Data Input b Data
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 69 69 83 83 -- -- 69 69 83 83 -- -- 69 79 83 96 -- -- 150 TA = +25C -- -- 150 TA = +85C Max. 150 Unit A mA Condition -- -- -- -- Min. Typ. Max. Min. Typ. Max. Min. Typ.
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0C Symbol tPLH tPHL Parameter Propagation Delay to Output D SEL1 SEL2 LEN MR Set-up Time D SEL1 SEL2 Hold Time D SEL1 SEL2 Reset Recovery Time Minimum Pulse Width, MR Within-Device Skew Rise/Fall Time 20% to 80% TA = +25C TA = +85C Max. 900 1050 900 800 825 ps 400 600 500 300 100 200 700 400 -- 275 275 300 250 -275 -300 -250 600 -- 50 475 -- -- -- -- -- -- -- -- -- 700 400 600 500 300 100 200 700 400 -- 275 275 300 250 -275 -300 -250 600 -- 50 475 -- -- -- -- -- -- -- -- -- 700 400 600 500 300 100 100 700 400 -- 275 275 300 250 -275 -300 -250 600 -- 50 475 -- -- -- ps -- -- -- -- -- -- 700 ps ps ps ps -- -- 1 -- -- -- Unit ps 400 550 450 350 350 600 775 650 500 600 900 1050 900 800 825 400 550 450 350 350 600 775 650 500 600 900 1050 900 800 825 400 550 450 350 350 600 775 650 500 600 Condition -- Min. Typ. Max. Min. Typ. Max. Min. Typ.
tS
tH
tRR tPW tskew tr tf
NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device.
PRODUCT ORDERING CODE
Ordering Code SY10E256JC SY10E256JCTR SY100E256JC SY100E256JCTR 2 Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial
Micrel
SY10E256 SY100E256
28 LEAD PLCC (J28-1)
Rev. 03
3
Micrel
SY10E256 SY100E256
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
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